名稱：3線8線譯碼器74LS138設計（代碼在文末付費下載）

軟件：QuartusII

語言：VHDL

代碼功能：

3線8線譯碼器74LS138的設計

使用VHDL代碼

74138

演示視頻：

FPGA代碼Verilog/VHDL代碼資源下載網(wǎng)：www.hdlcode.com

部分代碼展示

LIBRARY?ieee;
???USE?ieee.std_logic_1164.all;
ENTITY?LS138?IS
???PORT?(
??????A0??:?IN?STD_LOGIC;
??????A1??:?IN?STD_LOGIC;
??????A2??:?IN?STD_LOGIC;
??????
??????S1??:?IN?STD_LOGIC;
??????S2??:?IN?STD_LOGIC;
??????S3??:?IN?STD_LOGIC;
??????
??????Y7??:?OUT?STD_LOGIC;
??????Y6??:?OUT?STD_LOGIC;
??????Y5??:?OUT?STD_LOGIC;
??????Y4??:?OUT?STD_LOGIC;
??????Y3??:?OUT?STD_LOGIC;
??????Y2??:?OUT?STD_LOGIC;
??????Y1??:?OUT?STD_LOGIC;
??????Y0??:?OUT?STD_LOGIC
???);
END?LS138;
ARCHITECTURE?behave?OF?LS138?IS
???
???SIGNAL?A_data?:?STD_LOGIC_VECTOR(2?DOWNTO?0);
???SIGNAL?Y_data?:?STD_LOGIC_VECTOR(7?DOWNTO?0)?:=?"00000000";
BEGIN
???A_data?<=?(A2?&?A1?&?A0);
???Y7?<=?Y_data(7);
???Y6?<=?Y_data(6);
???Y5?<=?Y_data(5);
???Y4?<=?Y_data(4);
???Y3?<=?Y_data(3);
???Y2?<=?Y_data(2);
???Y1?<=?Y_data(1);
???Y0?<=?Y_data(0);
???
???PROCESS?(S1,?S2,?S3,?A_data)
???BEGIN

設計文檔：

1.功能要求

2.工程文件

3.程序文件

4.程序編譯

5.仿真程序（testbench）

6.仿真圖

點擊鏈接獲取代碼文件：http://www.hdlcode.com/index.php?m=home&c=View&a=index&aid=225